Disturb-proof static RAM cells
US9558811B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Aug 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a latch circuit, a buffer transistor having a control terminal coupled to a first output of the latch, a first write transistor having a conduction terminal coupled to the first output and a control terminal coupled to a first write bitline, and a second write transistor having a conduction terminal coupled to a second output of the latch and a control terminal coupled to a second write bitline. A method of operating a memory cell circuit includes providing a first value on first and second write bitlines when a read operation is performed, and when a write operation is performed, providing first and second values on the first and second write bitlines, respectively, when a first storable value is to be stored, and providing the first and second value on the second and first write bitlines, respectively, when a second storable value is to be stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.