Method of fabricating low CTE interposer without TSV structure
US9558964B2 · kind B2 · utility
0Cited by
42References
19Claims
0Family size
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Key dates
| Filing date | Oct 27, 2014 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Oct 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.