Method for manufacturing in a semiconductor device a low resistance via without a bottom liner
US9559051B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2015 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Dec 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.