Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors
US9559134B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2014 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.