Vertical transistor for resistive memory
US9559297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2016 |
| Grant date | Jan 31, 2017 |
| Priority date | — |
| Expiry date | Jul 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/245
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of making a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.