Partial block erase for data refreshing and open-block programming
US9563504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.