High capacity memory systems with inter-rank skew tolerance

US9563597B2 · kind B2 · utility

Assignee

• Rambus Inc. · US

Inventors

• Frederick A. Ware · Los Altos Hills, US
• Ely Tsern · Los Altos, US
• Brian S. Leibowitz · San Francisco, US
• Wayne F. Ellis · Campbell, US
• Akash Bansal · Santa Clara, US
• John Brooks · San Jose, US
• Kishore Ven Kasamsetty · Cupertino, US

Key dates

• Filing date: Dec 20, 2012
• Grant date: Feb 7, 2017
• Expiry date: May 13, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.