Structures and methods for extraction of device channel width
US9564375B2 · kind B2 · utility
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11References
18Claims
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Key dates
| Filing date | Oct 15, 2013 |
| Grant date | Feb 7, 2017 |
| Priority date | — |
| Expiry date | Oct 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B2210/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.