Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures

US9564575B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Danny Pak-Chum Shum · Poughkeepsie, US
• Hai Cong · Singapore, SG
• Yi Jiang · Singapore, SG
• Juan Boon Tan · Singapore, SG

Key dates

• Filing date: Dec 30, 2014
• Grant date: Feb 7, 2017
• Expiry date: Mar 5, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/10

Abstract

Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.