Structure and method for testing stacked CMOS structure
US9568543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2013 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.