Method of integrated circuit scan clock domain allocation and machine readable media thereof
US9568553B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Sep 16, 2013 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.