Controller to manage NAND memories
US9569129B2 · kind B2 · utility
1Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.