Reduced-overhead error detection and correction
US9569308B1 · kind B1 · utility
10Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.