Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
US9569363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jul 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.