Data aware write scheme for SRAM
US9570156B1 · kind B1 · utility
17Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Aug 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.