1D-2R memory architecture
US9570165B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.