Memory page buffer
US9570186B2 · kind B2 · utility
0Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.