Gate fringing effect based channel formation for semiconductor device

US9570458B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Youseok Suh · Cupertino, US
• Sung-Yong Chung · Davis, US
• Ya-Fen Lin · Saratoga, US
• Yi-Ching Wu · Hengshan, TW

Key dates

• Filing date: Feb 12, 2014
• Grant date: Feb 14, 2017
• Expiry date: Feb 12, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.