Gate and gate forming process
US9570578B2 · kind B2 · utility
1Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.