Method of forming split gate memory cells with 5 volt logic devices

US9570592B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Nhan Do · Saratoga, US
• Vipin Tiwari · Dublin, US

Key dates

• Filing date: May 25, 2016
• Grant date: Feb 14, 2017
• Expiry date: May 25, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.