On chip detection of electrical overstress events
US9575111B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Aug 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/202
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.