Memory device with reduced test time
US9575125B1 · kind B1 · utility
16Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jun 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31718
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.