Deadlock/livelock resolution using service processor
US9575816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2013 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Sep 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a main processor and a service processor. The service processor is configured to detect and break a deadlock/livelock condition in the main processor. The service processor detects the deadlock/livelock condition by detecting the main processor has not retired an instruction or completed a processor bus transaction for a predetermined number of clock cycles. In response to detecting the deadlock/livelock condition in the main processor, the service processor causes arbitration requests to a cache memory to be captured in a buffer, analyzes the captured requests to detect a pattern that may indicate a bug causing the condition and performs actions associated with the pattern to break the deadlock/livelock. The actions include suppression of arbitration requests to the cache, suppression of comparisons cache request addresses and killing requests to access the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.