Read-current and word line delay path tracking for sense amplifier enable timing
US9576621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2013 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.