Etching chamber with subchamber
US9576824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2006 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67751
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first chamber (103). The combination of the semiconductor wafer or sample and the sample holder is enclosed within a second chamber (130) inside the first chamber. Gas is evacuated from the second chamber and an etching gas is introduced into the second chamber, but not into the first chamber, to etch the semiconductor wafer or sample.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.