Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same
US9576894B2 · kind B2 · utility
7Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 3, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.