Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques
US9582629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Apr 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.