Jongwook Kye
88Patents
13h-index
60Co-inventors
83Inventor score
Filing activity: Sep 14, 2000 → Jan 4, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6489068B1 | Process for observing overlay errors on lithographic masks | Physics | 63 | Expired |
| US8889561B2 | Double sidewall image transfer process | Electricity | 39 | Active |
| US7315033B1 | Method and apparatus for reducing biological contamination in an immersion lithography system | Physics | 38 | Expired |
| US8741763B2 | Layout designs with via routing structures | Electricity | 32 | Active |
| US8954913B1 | Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules | Physics | 30 | Active |
| US8921225B2 | Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology | Electricity | 18 | Active |
| US6555274B1 | Pupil filtering for a lithographic tool | Physics | 18 | Expired |
| US8581348B2 | Semiconductor device with transistor local interconnects | Electricity | 17 | Active |
| US6829040B1 | Lithography contrast enhancement technique by varying focus with wavelength modulation | Physics | 17 | Expired |
| US8881083B1 | Methods for improving double patterning route efficiency | Electricity | 16 | Active |
| US9437588B1 | Middle of-line architecture for dense library layout using M0 hand-shake | Electricity | 15 | Active |
| US9818651B2 | Methods, apparatus and system for a passthrough-based architecture | Electricity | 14 | Active |
| US6399401B1 | Test structures for electrical linewidth measurement and processes for their formation | Emerging Cross-Sectional Technologies | 14 | Expired |
| US9431300B1 | MOL architecture enabling ultra-regular cross couple | Electricity | 13 | Active |
| US6556286B1 | Inspection system for the pupil of a lithographic tool | Physics | 13 | Expired |
| US8918746B1 | Cut mask aware contact enclosure rule for grating and cut patterning solution | Electricity | 13 | Active |
| US9324722B1 | Utilization of block-mask and cut-mask for forming metal routing in an IC device | Electricity | 12 | Active |
| US6710853B1 | Phase grating focus monitor using overlay technique | Physics | 12 | Expired |
| US9105510B2 | Double sidewall image transfer process | Electricity | 12 | Active |
| US9202751B2 | Transistor contacts self-aligned in two dimensions | Electricity | 11 | Active |
| US9147653B2 | Method for off-grid routing structures utilizing self aligned double patterning (SADP) technology | Electricity | 11 | Active |
| US8802574B2 | Methods of making jogged layout routings double patterning compliant | Physics | 11 | Active |
| US6602794B1 | Silylation process for forming contacts | Electricity | 10 | Expired |
| US8839168B2 | Self-aligned double patterning via enclosure design | Physics | 10 | Active |
| US6535280B1 | Phase-shift-moiré focus monitor | Physics | 10 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.