Reading resistive random access memory based on leakage current
US9583183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.