Integrated circuit structure and method for reducing polymer layer delamination
US9583424B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 23, 2013 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | May 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.