Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
US9583442B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.