Three-dimensional semiconductor device and method of manufacturing the same
US9583503B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Dec 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor device is provided, comprising: a plurality of ground selection line (GSL) sections separately formed on a substrate, the GSL sections being electrically insulated from each other and extended in parallel to each other, and the GSL sections extending along a first direction; a plurality of stacked structures vertically formed on the GSL sections on the substrate, and each stacked structure comprising alternated semiconductor layers and insulating layers; string selection lines (SSLs) separately formed on the stacked structures, and the string selection lines extending along the first direction; and bit lines disposed above the SSLs and extending along a second direction, the bit lines arranged parallel to each other and in perpendicular to the SSLs and GSL sections, wherein a plurality of memory cells of memory layers respectively defined by the stacked structures, the SSLs, the GSL sections and the bit lines correspondingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.