Transient voltage suppressor (TVS) with reduced breakdown voltage
US9583586B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.