Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure

US9583640B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ralf Richter · Dresden, DE
• Sven Beyer · Dresden, DE
• Carsten Grass · Dresden, DE
• Tom Herrmann · Dresden, DE

Key dates

• Filing date: Dec 29, 2015
• Grant date: Feb 28, 2017
• Expiry date: Dec 29, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6893

Abstract

A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.