Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
US9588771B2 · kind B2 · utility
1Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Sep 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.