Array of processor core circuits with reversible tiers
US9588937B2 · kind B2 · utility
5Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2013 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Mar 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.