Reducing programming disturbance in memory devices
US9589644B2 · kind B2 · utility
8Cited by
5References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 8, 2012 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.