Disturb free bitcell and array

US9589658B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Navin Agarwal · Sherghati, IN
• Aditya S. Auyisetty · Bengaluru, IN
• Balaji Jayaraman · Coventry, GB
• Thejas Kempanna · Bengaluru, IN
• Toshiaki Kirihata · Poughkeepsie, US
• Ramesh Raghavan · Hyderabad, IN
• Krishnan S. Rengarajan · Bengaluru, IN
• Rajesh Reddy Tummuru · Bengaluru, IN
• Jay M. Shah · Bengaluru, IN
• Janakiraman Viraraghavan · Bengaluru, IN

Key dates

• Filing date: Aug 18, 2015
• Grant date: Mar 7, 2017
• Expiry date: Aug 18, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/02
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.