Method for eliminating interlayer dielectric dishing and controlling gate height uniformity
US9589807B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | May 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.