3D integration of fanout wafer level packages
US9589936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.