Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly under the staircase
US9589978B1 · kind B1 · utility
45Cited by
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26Claims
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Key dates
| Filing date | Feb 25, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Feb 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs of the flight of stairs are respectively coupled to different tiers of memory cells, and a different pass transistor of the plurality of pass transistors is coupled to each of the stairs of the flight of stairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.