Vertical FET having reduced on-resistance
US9590096B2 · kind B2 · utility
2Cited by
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20Claims
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Assignee
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Key dates
| Filing date | Nov 16, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over the drift region and having source diffusions formed therein, a gate trench extending through the body region, and channel regions adjacent the gate trench. The channel regions are spaced apart along the gate trench by respective deep body implants. Each of the deep body implants is situated approximately under at least one of the source diffusions, and has a depth greater than a depth of the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.