Load/store operations in texture hardware

US9595075B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Steven James Heinrich · Huntsville, US
• Eric T. Anderson · Palo Alto, US
• Jeffrey A. Bolz · Austin, US
• Jonathan Dunaisky · Fort Collins, US
• Ramesh Jandhyala · Austin, US
• Joel J. McCormack · Boulder, US
• Alexander L. Minkin · Los Altos, US
• Bryon S. Nordquist · Santa Clara, US
• Poornachandra Rao · Cedar Park, US

Key dates

• Filing date: Sep 26, 2013
• Grant date: Mar 14, 2017
• Expiry date: May 31, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/302
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.