Memory array having connections going through control gates
US9595533B2 · kind B2 · utility
11Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Dec 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.