Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies
US9595536B1 · kind B1 · utility
12Cited by
4References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Apr 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s), and includes 13-CPP and 17-CPP D flip-flop cells, is disclosed, along with wafers, chips and systems constructed from such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.