Field effect transistor and method of fabricating the same
US9595610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2015 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | May 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.