Structural testing of integrated circuits
US9599673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Sep 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31908
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.