Common platform for one-level memory architecture and two-level memory architecture
US9600413B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2013 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.