Trench formation for dielectric filled cut region
US9601335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.