3D NAND staircase CD control by using interferometric endpoint detection
US9601396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.